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The TechArena presents Edge 2023, Seven Strategies for Maximizing Organizational Return based on interviews with Arm, Avassa, Canonical, Cellnex, Dell, Future of Privacy Forum, Intel, MIT, Nvidia, Radware, Ribbon, Scale Computing, and Varnish Software.

TechArena host Allyson Klein chats with Ampere CPO Jeff Wittich and HPE VP Peter Groth about their recently announced collaboration for cloud infrastructure optimized for compute sustainability.

TechArena host Allyson Klein chat’s with OCP’s VP of Market Intelligence and Innovation, Cliff Grossner, about the challenges facing data center innovation and how OCP has transformed to drive deeper partnerships with the industry and broaden its impact on data center innovation.

TechArena host Allyson Klein chats with Avassa CTO Carl Moberg about how his company is bringing application control to edge environments and how his team as designed solutions for both infrastructure operators and application developers.

TechArena host Allyson Klein chats with OCP Chair and CloudFlare VP Rebecca Weekly about the future of open computing solutions, how regional demands drive the OCP mission, and the importance of sustainability.

TechArena Host Allyson Klein chats with Open Compute Foundation leaders Michael Schill and Steve Helvie about the organization’s rising contributions and what it means for broad adoption of open hardware configurations from edge to cloud.

TechArena host Allyson Klein chats with OpenUK CEO Amanda Brock live from the OCP Regional Summit in Prague on her organization’s mission to drive open software, hardware and data contributions for UK developers.

TechArena host Allyson Klein chats with Varnish CMO Adrian Herrera about the demand for higher performance content delivery at the edge and how his company is investing in record breaking technology breakthroughs to fuel customer requirements.

TechArena host Allyson Klein chats with Oracle VP Shasank Chavan about in-memory databases, customer demands in a data centric world, and how infrastructure must change to fuel customer needs.

TechArena host Allyson Klein chats with Scale Computing VP Craig Theriac about his company’s vision for simplified edge deployments for any environment and how Scale Computing solutions have evolved to meet evolving market demands.

We are entering a golden age of silicon innovation with disruptive innovation shaping how the foundations of computing will be designed, delivered, and deployed at scale. This is an area of the computing landscape that the TechArena has invested more than a fair share of time with expert discussions on CXL and UCIe, two industry standards that aim to change the face of data center infrastructure as we’ve known it for the past quarter century. This is why I was delighted to catch up with Letizia Giuliano, Alphawave Semi’s vice president of IP and product management, at the MemCon conference in Mountain View, California.

Alphawave Semi has emerged as a leader in high speed connectivity IP and silicon, and while they were focused on their HBM solutions at MemCon, their ambitions are much broader moving into IP blocks that can extend from data center SSD delivery to optics to future chiplet designs for UCIe powered compute. Letizia is a veteran of semiconductor design having worked on the complex and innovative Ponte Vecchio solution at Intel before joining Alphawave Semi, and our conversation was insightfully reflective of a new breed of semi innovator that is focusing on delivering core capabilities really well to fuel optimal package delivery.

Giuliano explained the company’s strategy is very much fueled by the AI era and the demand from customers to deliver more data to compute faster to speed time to insight from larger and larger data sets. HBM provides a perfect example of where Alphawave Semi’s expertise comes into play. “HBM is based on a 3D stack technology, so takes advantage of the new processes like TSB and 3D packaging and allows an SOC to have a wide part of the bus faster delivering higher bandwidth that differentiates it from other types of traditional DDR memory like DDR5 and DDR6.” This industry standard 3D stacked delivery of a wider memory bus provided by Alphawave Semi allows customers to take advantage of a lower latency and higher bandwidth memory source for data hungry application performance.

But that’s just the beginning. Alphawave Semi has set its sites squarely on the enormous opportunity that the UCIe standard has unleashed to the industry, for the first time creating a standard interconnect for chiplets on the same die. Giuliano’s excitement about what UCIe represents for her company was palpable in our discussion. “Someone said that the package is going to be the next motherboard and I really relate to that. Alphawave Semi can build a lot of pieces inside that package to make sure that we accelerate time to market for the solution.” This vision opens up incredible opportunity for disruptive platforms for customers like the large cloud service providers deeply involved in the UCIe standard, but it also changes the landscape of smaller semiconductor players with unique niches becoming increasingly relevant in delivery of IP to multi-vendor designs. This is what makes Alphawave Semi and others like them in the industry so interesting as we make this bold foray into the new chiplet era of compute delivery. To check out more about Alphawave Semi and get in touch with the team visit their website. As always, thanks for engaging - Allyson

TechArena host Allyson Klein chats with Alphawave Semi’s Letizia Guiliano about the future of semiconductor innovation across memory, optical and interoperable chiplet solutions and how her company is poised to deliver leadership innovation rooted in standards.

As we wrap the first quarter of 2023 we are facing an environment of soft demand for data center infrastructure and questions about DRAM innovation. Traditional DRAM technologies are pushing up against traditional cell shrink expectations with the demise of Moore’s Law and innovation cost recovery delayed from traditional one generation cadence. Price curves on DRAM have also taken a hit from soft demand looking like double diamond ski slopes for the last couple of quarters. In fact, as the industry discussed the state of memory yesterday in Mountain View, Micron announced the worst loss in the history of the company due to memory write offs but also signaled that the epic fall may be behind us providing a glimmer of hope for demand stabilization. With this subdued current state of affairs, I don’t think there’s a better time to look to the future where disruptive paths of innovation will help propel this entire sector forward and bring the data capacity and performance capability AI era applications demand.

In today’s MemCon Keynote, Microsoft’s Zaid Khan laid out the challenge clearly. AI workloads require massive memory footprints, and while HBM solutions hold promise for the performance AI requires, issues with error sustainability and capacity may limit its application. New alternatives are required. Zaid called for radical scaling solution alternatives to be created by the industry that address not only performance and speed/bandwidth requirements but also break through on geometry and TCO challenges facing today’s traditional innovation curve with new memory hierarchies.

All Industry Innovation Leads to CXL

While there was talk of new memory tiering with HBM and accelerated memory in the MemCon presentations, the behemoth in the room at the conference was CXL. The new industry standard available on both Intel and AMD platforms today and gaining traction with industry solution availability promises to introduce a new tier of memory for additional tiering of memory for applications not requiring the low latency of DDR5 or even HBM configurations. CXL will also open the door for disaggregated system design functioning as a switch connecting compute pools with coherent memory pools and enabling workload composability with resource precision we’ve not historically seen in data centers. The good news about CXL? The large cloud providers are squarely behind the technology serving on the board for the standards consortium and placing their weight behind integration of the standard into their infrastructure. This matters…a lot…when you consider the volume of infrastructure the large players represent to the market.

But questions still remain. Will CXL’s reliance on PCIe gen 5 and 6 provide the data rates required for tiered memory solutions, or will latency drawbacks gate use by many applications? What happens to the enterprise? Do they have sophisticated enough workload oversight for on-prem use of this new capability at scale, and will CXL’s introduction form an even greater wedge between cloud provider and enterprise data center environments? And can CPU vendors deliver on schedule to ensure the swift transition to the “now it really gets interesting” flavors of the specification, namely introduction of CXL 2.0 and 3.0 in servers? Intel and AMD are both on the record for integration of 2.0 in next generation servers, and the collective assembled in Mountain View certainly hope that they both deliver to promises as their delivery is required for broad market adoption. As always, thanks for reading - AK

TechArena host Allyson Klein chats with Memverge founder and CEO Charles Fan about his company’s disruptive vision for breaking through data center memory limitations and what the CXL standard will bring to infrastructure innovation.

TechArena host Allyson Klein chats with AMD senior fellow and CXL technical taskforce co-chair Mahesh Wagh regarding AMD’s entry of CXL platforms into the market gen 4 AMD EYPC processors and his organization’s strategy to deliver disruptive innovation utilizing CXL capability in the years ahead.

TechArena host Allyson Klein chats with Arm’s Panch Chandrasekaran about the massive opportunity for innovation at the edge of the network, need for efficiency for vRAN solutions, and his organization’s strategy to deliver disruptive innovation for providers.

TechArena host Allyson Klein chats with Radware CTO David Aviv about the unique challenges of securing the edge and how his company is shaping security solutions to minimize attack threats.

TechArena host Allyson Klein chats with Kartik Sawheny, founder of I-STEM, about his mission for delivering increased accessibility across computing and the challenges inherent in the industry today.

TechArena host Allyson Klein chats with Accenture’s Astha Bhardwaj on initial use cases of the metaverse emerging today and where Accenture sees immersive environments evolving in the future.

TechArena host Allyson Klein chats with Gabriela Zanfir-Fortuna of the Future of Privacy Forum about the state of data privacy and where the industry must plan for future policy alignment.

TechArena host Allyson Klein chats with Canonical’s Arno van Huyssteen and Wajeeha Hamid about the state of opensource for the network and their new solutions for RAN implementations.

TechArena host Allyson Klein chats with Ribbon’s Matt Hurst about the opportunity of 5G services at the edge and how they’re reshaping business.

TechArena host Allyson Klein chats with Cellnex’s Catherine Gull on the state of private 5G deployments and how her company is tapping the technology for deeper engagement with customers.

TechArena Host Allyson Klein discusses the imperatives for 6G as we head deep into standards definition and the need for collaboration between industry and academia on future standards with MIT’s Muriel Medard.

TechArena host Allyson Klein sits down with Dell VP Aaron Chaisson to discuss the company’s strategy for edge, current deployment trends, and a reveal of their new program for private 5G deployment.