Synopsys Brings Agentic AI to Chip Design on TSMC Nodes

The chips powering the next wave of AI infrastructure are getting harder to design. And the tools used to create them are starting to think for themselves.

Synopsys today announced a broad expansion of its collaboration with TSMC, spanning AI-powered EDA flows, silicon-proven IP across advanced and specialty nodes, and new design enablement for co-packaged optics. The announcement, timed to TSMC’s 2026 Technology Symposium in North America, covers TSMC’s 3nm and 2nm families along with A16 (with Super Power Rail) and A14. But the real headline sits in a single word that keeps surfacing across the semiconductor design world: agentic.

Agentic EDA Hits the Design Floor

Synopsys is collaborating with TSMC on what it calls “agentic run assistance” inside its Fusion Compiler, targeting TSMC’s A14 process using the NanoFlex Pro architecture. In practice, that means the tool can now identify timing improvement opportunities at different stages of the design flow on its own, rather than waiting for an engineer to manually intervene at each checkpoint. The goal: better power, performance, and area results with fewer human-in-the-loop iterations.

This is a meaningful step beyond the optimization work Synopsys has done with its DSO.ai technology over the past several years. Where DSO.ai focused on tuning parameters within a defined design space, agentic run assistance implies the tool is making multi-stage decisions about where and when to act across the flow. AI-assisted physical verification in Synopsys IC Validator is also progressing, aimed at accelerating the identification and resolution of design rule violations for faster tapeout quality.

The multiphysics signoff portfolio is expanding in parallel. Synopsys RedHawk-SC for digital power integrity, Totem-SC for analog power integrity, and HFSS-IC Pro for electromagnetic extraction now span TSMC nodes from A16 through A14. Totem-SC provides ultrahigh-capacity analog power integrity signoff for large N2-based designs, while PathFinder-SC extends multi-die electrostatic discharge signoff coverage to N2. Cloud-based multiprocessor and GPU acceleration shortens turnaround for teams iterating across thermally constrained 3D assemblies.

Multi-Die Design and a Broader IP Portfolio

Chip architectures are fragmenting by design. Multi-die systems built on advanced packaging let designers mix process nodes, integrate heterogeneous functions, and scale beyond the limits of a single monolithic die. Synopsys is leaning into that shift across both its EDA tools and its IP catalog.

The company’s 3DIC Compiler platform now supports TSMC’s CoWoS packaging technology at 5.5x reticle interposer sizes, a scale that tracks with the massive interposers shipping inside today’s flagship AI accelerators. As a unified exploration-to-signoff platform, 3DIC Compiler integrates with RedHawk-SC, RedHawk-SC Electrothermal, and Ansys HFSS software to deliver multiphysics analysis for thermal, power, and high-speed signal integrity in one environment.

On the IP side, Synopsys announced several firsts. Its UCIe IP ASIL B solution on TSMC’s N5A process is the only end-to-end IP of its kind designed for safety-critical automotive multi-die systems, a category that barely existed two years ago but is gaining real traction as automakers adopt chiplet architectures. The company also completed silicon bring-up of the industry’s first low-power M-PHY v6.0 IP on TSMC’s N2P process, pushing next-generation storage connectivity forward for smartphones and mobile applications. Across TSMC’s N5, N3P, and N2P processes, Synopsys achieved first-silicon milestones on PCIe 7.0, HBM4, 224G, DDR5 MRDIMM Gen2, LPDDR6/5X/5, UCIe 64G, and M-PHY v6.0 IP.

Co-Packaged Optics Gets a Design Tool Chain

Perhaps the most forward-looking piece of the announcement is Synopsys’ multiphysics design enablement for COUPE, TSMC’s co-packaged optics platform. The enablement spans Ansys Zemax OpticStudio for optical path simulation, Ansys Lumerical for photonic device simulation, HFSS-IC Pro for electromagnetic extraction, and RedHawk-SC Electrothermal for thermal and electrical co-simulation.

Synopsys also introduced a 224G IP solution that supports co-packaged optical Ethernet and UALink, targeting the bandwidth demands of next-generation electro-optical systems in AI data centers.

When an EDA vendor starts building full simulation flows for a technology, it signals that commercialization is no longer theoretical. Co-packaged optics has been a conference-circuit favorite for years. Now it has a design tool chain.

The TechArena Take

Three threads in this announcement deserve attention beyond the product specifics.

First, the agentic language matters. The semiconductor industry is moving past AI-as-optimizer toward AI-as-collaborator in the design flow. Synopsys is not alone in this pursuit, but its depth of integration with TSMC’s most advanced nodes gives it a proving ground that few competitors can match. If agentic run assistance delivers measurable PPA gains on A14, expect the rest of the EDA ecosystem to accelerate their own autonomous workflow roadmaps.

Second, the Ansys acquisition is paying visible dividends. The multiphysics coverage in this announcement, spanning optical, electromagnetic, thermal, and electrical simulation, would not have been possible under one roof before the merger closed. That vertical integration from RTL to photonics simulation is becoming a genuine differentiator, particularly as chip designs grow more three-dimensional and multi-domain.

Third, the co-packaged optics enablement is a quiet signal worth watching. Bandwidth scaling in AI clusters is approaching the practical limits of electrical interconnects. The fact that Synopsys, TSMC, and the Ansys simulation stack are now aligned on COUPE design flows suggests the industry’s timeline for production co-packaged optics may be shorter than many assume. The 224G IP supporting both optical Ethernet and UALink adds a concrete building block to what has, until recently, been mostly a research narrative.

Taken together, this announcement reflects a broader truth about the AI infrastructure buildout: the tools that design AI chips are themselves becoming AI-driven, and the companies that control that feedback loop will shape how fast the next generation of silicon reaches production.