Automotive Meets Chiplets: Robert Bielby’s Perspective on the Impact of Level 3 ADAS on Emerging Semiconductor Tech
While Level 3 ADAS (conditional automation) requires the driver to be present and engaged, the resultant heterogeneous workload, a mix of compute and AI processing, is driving the need for new system-level architectures and state-of-the-art system-on-chips (SoCs) based upon leading-edge semiconductor processes and packaging technologies. More specifically, solutions for Level 3 ADAS and above are driving the automotive industry to embrace chiplets to most efficiently and effectively address the demanding workloads by allocating the right task to the right compute engine optimized for a given task in a footprint that is most efficient from both a power and area perspective. It is also the case that chiplet-based solutions can be more cost-effective when compared to an equivalent solution based on monolithic technologies.
Chiplet technology, still in its relative infancy, enables disparate technologies and semiconductor dice to be combined in a single package through the use of die-to-die interconnect which is physically connected via a package substrate while enabling performance that is equivalent to that of a monolithic device.
In March 2022, a universal interface for the interconnection of chiplets was released. Dubbed UCIe 1.0 (Universal Chiplet Interconnect Express), the introduction of this standard, in part, reflects the broader industry awareness that the traditional benefits of scaling through process technology are being challenged. To be clear, the major semiconductor foundries continue to invest heavily in developing advanced process nodes which continue to offer improved power, performance, and area benefits. However, the economics of these advanced nodes present significant barriers to adoption for a large percentage of the ASIC / ASSP design community. Additionally, the benefits of scaling associated with migrating to the most advanced semiconductor process node do not apply uniformly across all circuit types - most notably analog circuits.
As such, while scaling through Moore’s law is still a very important vector for the semiconductor industry, the move to chiplets and the use of advanced packaging technologies are rapidly becoming an important vector for the industry - and in fact, hold the promise of spawning a new industry where chiplets from different vendors can be readily interconnected via UCIe to rapidly build new products that combine best in class technologies into a single package delivering fast time to market, low risk, and low development cost. The benefits of chiplets are quite meaningful enabling the following benefits:
- Ability to build SoCs that are larger than the reticle of the semiconductor manufacturing equipment
- Building SoCs with higher yield and correspondingly lower cost vs. monolithic solutions
- Reduced R&D cost vs. employing advanced nodes
- Accelerated time to market
- Smaller footprint - vs. discrete two-chip solution
- Higher performance vs. discrete two-chip solution
- Lower power vs. discrete two-chip solution
UCIe is an open specification that defines the interconnect between chiplets within a package, enabling the formation of a chiplet ecosystem with a common interconnect footprint at the package level. In effect, through industry standardization, the equivalent of a common footprint, similar to Lego®, is being established. The UCIe standard is endorsed by 72 contributing members, and 26 adopting members at the time of this writing.
The initial focus of the UCIe 1.0 specification was in the following areas
- Physical Layer: Die-to-Die I/O with industry-leading Key Performance Indicators (KPIs)
- Protocol: CXL/PCIe for near-term volume attach
- Well-defined specification: ensure interoperability & evolution
The UCIe physical layer supports I/Os that can provide up to 32 Giga Transfers per second (GTs) with 16 to 64 lanes and uses a 256-byte Flow Control Unit for data, similar to PCIe 6.0. The protocol layer is based on Compute Express Link (CXL). In short, UCIe is leveraging tried and tested technologies that have a strong legacy of adoption across many markets.
As a testament to the importance of UCIe to the automotive industry, In August of 2023, the UCIe consortia introduced a 1.1 version of the specification with a focus on the following areas:
- Enhancement for automotive - including runtime health monitoring and repair for high-reliability applications
- New usages for streaming protocols with full UCIe stack
- Protocol support with end-to-end link layer functionality
- Cost optimization for advanced packaging resulting from new bump maps
- Enhancements for compliance testing
While all of these components of the 1.1 specification reflect a keen focus on the critical next-level details associated with chip-to-chip interconnectivity and device-to-device communication, the specific considerations for automotive applications in the UCIe 1.1 specification underscore the strong anticipated adoption of chiplets in safety-critical automotive applications.
Addressing those safety concerns, the UCIe 1.1 version of the specification includes preventive monitoring to ensure that the die-to-die signaling “eye” height and width are optimal and can be re-trained as needed. (As a note, the “eye” diagram is a way to measure the signal integrity of the link. The more open the “eye” is, the greater the signal integrity). There is also the addition of run-time testability of link health which includes the periodic parity Flit injection checking for the health monitoring of each lane with the ability to repair as required.
The adoption of state-of-the-art technologies marks a sea change in the automotive industry where historically, automotive electronics employed mature products that were typically based on mature semiconductor process technologies. With the advent of ADAS and AD, this has now changed. AI performance requirements that can reach PetaOPs levels for Level 5 ADAS are best addressed via heterogeneous computing solutions employing high energy-efficient, high-TOPs AI accelerators in a chiplet form factor.
At the time of this writing, the UCIe consortia is preparing to release a 2.0 version of the specification. When the results are made publicly available, we will take a look and see what additional features and considerations have been made to the specification and place a focus on those that specifically address the automotive market.
While Level 3 ADAS (conditional automation) requires the driver to be present and engaged, the resultant heterogeneous workload, a mix of compute and AI processing, is driving the need for new system-level architectures and state-of-the-art system-on-chips (SoCs) based upon leading-edge semiconductor processes and packaging technologies. More specifically, solutions for Level 3 ADAS and above are driving the automotive industry to embrace chiplets to most efficiently and effectively address the demanding workloads by allocating the right task to the right compute engine optimized for a given task in a footprint that is most efficient from both a power and area perspective. It is also the case that chiplet-based solutions can be more cost-effective when compared to an equivalent solution based on monolithic technologies.
Chiplet technology, still in its relative infancy, enables disparate technologies and semiconductor dice to be combined in a single package through the use of die-to-die interconnect which is physically connected via a package substrate while enabling performance that is equivalent to that of a monolithic device.
In March 2022, a universal interface for the interconnection of chiplets was released. Dubbed UCIe 1.0 (Universal Chiplet Interconnect Express), the introduction of this standard, in part, reflects the broader industry awareness that the traditional benefits of scaling through process technology are being challenged. To be clear, the major semiconductor foundries continue to invest heavily in developing advanced process nodes which continue to offer improved power, performance, and area benefits. However, the economics of these advanced nodes present significant barriers to adoption for a large percentage of the ASIC / ASSP design community. Additionally, the benefits of scaling associated with migrating to the most advanced semiconductor process node do not apply uniformly across all circuit types - most notably analog circuits.
As such, while scaling through Moore’s law is still a very important vector for the semiconductor industry, the move to chiplets and the use of advanced packaging technologies are rapidly becoming an important vector for the industry - and in fact, hold the promise of spawning a new industry where chiplets from different vendors can be readily interconnected via UCIe to rapidly build new products that combine best in class technologies into a single package delivering fast time to market, low risk, and low development cost. The benefits of chiplets are quite meaningful enabling the following benefits:
- Ability to build SoCs that are larger than the reticle of the semiconductor manufacturing equipment
- Building SoCs with higher yield and correspondingly lower cost vs. monolithic solutions
- Reduced R&D cost vs. employing advanced nodes
- Accelerated time to market
- Smaller footprint - vs. discrete two-chip solution
- Higher performance vs. discrete two-chip solution
- Lower power vs. discrete two-chip solution
UCIe is an open specification that defines the interconnect between chiplets within a package, enabling the formation of a chiplet ecosystem with a common interconnect footprint at the package level. In effect, through industry standardization, the equivalent of a common footprint, similar to Lego®, is being established. The UCIe standard is endorsed by 72 contributing members, and 26 adopting members at the time of this writing.
The initial focus of the UCIe 1.0 specification was in the following areas
- Physical Layer: Die-to-Die I/O with industry-leading Key Performance Indicators (KPIs)
- Protocol: CXL/PCIe for near-term volume attach
- Well-defined specification: ensure interoperability & evolution
The UCIe physical layer supports I/Os that can provide up to 32 Giga Transfers per second (GTs) with 16 to 64 lanes and uses a 256-byte Flow Control Unit for data, similar to PCIe 6.0. The protocol layer is based on Compute Express Link (CXL). In short, UCIe is leveraging tried and tested technologies that have a strong legacy of adoption across many markets.
As a testament to the importance of UCIe to the automotive industry, In August of 2023, the UCIe consortia introduced a 1.1 version of the specification with a focus on the following areas:
- Enhancement for automotive - including runtime health monitoring and repair for high-reliability applications
- New usages for streaming protocols with full UCIe stack
- Protocol support with end-to-end link layer functionality
- Cost optimization for advanced packaging resulting from new bump maps
- Enhancements for compliance testing
While all of these components of the 1.1 specification reflect a keen focus on the critical next-level details associated with chip-to-chip interconnectivity and device-to-device communication, the specific considerations for automotive applications in the UCIe 1.1 specification underscore the strong anticipated adoption of chiplets in safety-critical automotive applications.
Addressing those safety concerns, the UCIe 1.1 version of the specification includes preventive monitoring to ensure that the die-to-die signaling “eye” height and width are optimal and can be re-trained as needed. (As a note, the “eye” diagram is a way to measure the signal integrity of the link. The more open the “eye” is, the greater the signal integrity). There is also the addition of run-time testability of link health which includes the periodic parity Flit injection checking for the health monitoring of each lane with the ability to repair as required.
The adoption of state-of-the-art technologies marks a sea change in the automotive industry where historically, automotive electronics employed mature products that were typically based on mature semiconductor process technologies. With the advent of ADAS and AD, this has now changed. AI performance requirements that can reach PetaOPs levels for Level 5 ADAS are best addressed via heterogeneous computing solutions employing high energy-efficient, high-TOPs AI accelerators in a chiplet form factor.
At the time of this writing, the UCIe consortia is preparing to release a 2.0 version of the specification. When the results are made publicly available, we will take a look and see what additional features and considerations have been made to the specification and place a focus on those that specifically address the automotive market.
